RESEARCHER

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Dr. Wutthinan Jeamsaksiri

Researcher

 
 

arrow E-mail : wutthinan.jeamsaksiri@nectec.or.th

arrow Telephone : +66 38 857-100 ext. 136

 

Roles and Responsibilities

Si CMOS based device process integration

 

Research Interests

Device and process design and integration and device electrical characterization

 

Selected Publications

Jeamsaksiri, W.; Jurczak, M.; Grau, L.; Linten, D.; Augendre, E.; De Potter, M.; Rooyackers, R.; Wambacq, P.; Badenes, G., “Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors,” Electron Devices, IEEE Transactions on Volume 50, Issue 3, March 2003 Page(s):610 - 617

 

Jeamsaksiri, W.; Mercha, A.; Ramos, J.; Linten, D.; Thijs, S.; Jenei, S.; Detcheverry, C.; Wambacq, P.; Velghe, R.; Decoutere, S., “Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA,” VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on 15-17 June 2004 Page(s):100 - 101

 

Jeamsaksiri, W.; Linten, D.; Thijs, S.; Carchon, G.; Ramos, J.; Mercha, A.; Sun, X.; Soussan, P.; Dehan, M.; Chiarella, T.; Venegas, R.; Subramanian, V.; Scholten, A.; Wambacq, P.; Velghe, R.; Mannaert, G.; Heylen, N.; Verbeeck, R.; Boullart, W.; Heyvaert, T.; Natarajan, M.I.; Groeseneken, G.; Debusschere, I.; Biesemans, S.; Decoutere, S., “A low-cost 90nm RF-CMOS platform for record RF circuit performance,” VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on 14-16 June 2005 Page(s):60 - 61

 

Jeamsaksiri, W.; Mercha, A.; Ramos, J.; Decoutere, S.; Cubaynes, F.N., “Optimal frequency range selection for full C-V characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide MOSFETs,” Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on 22-25 March 2004 Page(s):297 - 301

 

Bunjongpru, W.; Porntheeraphat, S.; Trithaveesak, O.; Somwang, N.; Khomdet, P.; Jeamsaksiri, W.; Hruanun, C.; Poyai, A.; Nukeaw, J., “The innovative AlN-ISFET based pH sensor,” Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, 2008. ECTI-CON 2008. 5th International Conference on Volume 2, 14-17 May 2008 Page(s):833 - 836

 

Post on 2009-06-11 | View 19933

OUR RESEARCH

OUR RESEARCH

Extraction of Defect in Doping Silicon Wafer by Analyzing the Lifetime Profile Method

Post on 2009-06-14

 

 

The total leakage current in silicon p-n junction diodes compatible with 0.8 μm CMOS technology is investigated. The generation lifetime is a key parameter for the leakage curre...

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